A Xilinx Spartan 3A chip can be programmed by using UrJTAG's pld command by fixing some issues related to old instructions. In this example, a Prometheus FPGA board is used. It is composed of a XC3S50A chip which can be configured by using FT-232H circuit's MPSSE mode. To start with, …
Embedded Systems
Remote Debugging of Native Android ARM 64-bit Executables Using gdbserver
In this tutorial, compilation and remote debugging of a simple C program on a rooted Android with ARM 64-bit architecture is described. The computer's hostname is ArchLinux and the smartphone Asus Zenfone is running on Android 5.0.2:
Install a cross-compiler toolchain
Install Android NDK (Native Development Kit):
4-bit Serial Adder/Subtractor with Parallel Load
This is a tutorial I wrote for the "Digital Systems Design" course as an introduction to sequential design. "4-bit Serial Adder/Subtractor with Parallel Load" is a simple project which may help to understand use of variables in the "process" statement in VHDL. However, basic understanding of the circuits is necessary, …
Using UrJTAG and OpenOCD to Write to a BSCAN Primitive on Xilinx Spatan 3 FPGAs
There are no tutorials explaining the use of BSCAN_SPARTAN3 primitive on Xilinx FPGAs. It's a very useful feature, which allows to literally establish a PC-to-FPGA link over a JTAG adapter. This primitive is already used in projects such as xc3sprog and Papilio-Loader to program SPI flash memory over JTAG.
BSCAN_SPARTAN3 …
Reading Device DNA on Spartan 3A chip
Among Spartan-3 generation of FPGAs only families 3A and 3AN have unique device identifier (device DNAs). DNA is a factory programmed unique 57-bit long number, whose the most significant bit is "1" and the second most significant bit is "0":
The Spartan 3A chip (xc3s50a) should be unconfigured (not loaded …
USERCODE Register in Xilinx Spartan 3E
The following setup was used for Basys2 board with an external FTDI-based JTAG adapter. Read the previous posts to get familiar with setup.
Specifying USERCODE
User code register provides bit stream identification and a type of version control. To write a user code into a bit stream in Xilinx ISE, …
Programming Basys2 Using xc3sprog and FTDI-Based JTAG Adapter
In order to program Basys2 board using xc3sprog and FTDI-Based JTAG Adapter, learn positions of the devices in the chain:
SVF Tutorial: Header and Trailing Registers Explained
Objective
This tutorial concerns with explaining use of some basic Serial Vector Format (SVF) instructions assuming that you are familiar with JTAG and TAP.
As an example, reading ID codes of the devices in a JTAG chain of the Digilent Basys2 FPGA board is given. A generic FTDI-MPSSE-based JTAG adapter …
Programming Basys2 Using OpenOCD and FTDI-Based JTAG Adapter
As a continuation of series of experiments with Basys2 board and FT232H-based JTAG adapter, I provide an easy way to generate SVF files for their further use in OpenOCD to program the board. No GUI interaction is needed, so it is saves a lot of time.
Programming the FPGA Chip
…Boundary Scan Operations with UrJTAG on Basys2 Development Board
UrJTAG is a good low-level tool to learn boundary scan operations and play with EXTEST, INTEST instructions. Assuming that the Basys2 board is connected to a UM232H-based JTAG adapter as described in the previous article, we can test EXTEST and INTEST instructions. Note that depending on package (VQ100, CP132, …
Connecting External FTDI-Based JTAG Adapter to Basys2 FPGA Board
I had a task to check whether OpenOCD can program a Spartan 3 series FPGA by means of FTDI-MPSSE-based JTAG adapter. There wasn't any chip available in my hands, so I had to experiment with existing hardware. I decided to solder the FTDI-based adapter to a Basys2 development board. The …