USERCODE Register in Xilinx Spartan 3E

The following setup was used for Basys2 board with an external FTDI-based JTAG adapter. Read the previous posts to get familiar with setup.

Specifying USERCODE

User code register provides bit stream identification and a type of version control. To write a user code into a bit stream in Xilinx ISE, go to "Implementation" -> "Design" and right-click on "Generate Programming File". In the popped up window specify your 32-bit user code in hexadecimal format:

For example, I set it to 0xADEAFBEE. Now generate the *.bit file in Xilinx ISE and analyze its header using bitparse utility, which is a part of xc3sprog:

UserID field tells that its value is embedded into the bit stream and will be written to the USERCODE during configuration.
Now program the FPGA using xc3sprog:


While your program is running on the FPGA, run UrJTAG:

The USERCODE instruction selects USERCODE register as data register. Shifting 32 bits into the data register will yield our user code.

Reading USERCODE in OpenOCD

While your program is running on the FPGA, start OpenOCD server:

In other terminal, connect as a client:

The user code is successfully retrieved.