This is a tutorial I wrote for the "Digital Systems Design" course as an introduction to sequential design. "4-bit Serial Adder/Subtractor with Parallel Load" is a simple project which may help to understand use of variables in the "process" statement in VHDL. However, basic understanding of the circuits is necessary, …
Tag Archives: VHDL
Using UrJTAG and OpenOCD to Write to a BSCAN Primitive on Xilinx Spatan 3 FPGAs
There are no tutorials explaining the use of BSCAN_SPARTAN3 primitive on Xilinx FPGAs. It's a very useful feature, which allows to literally establish a PC-to-FPGA link over a JTAG adapter. This primitive is already used in projects such as xc3sprog and Papilio-Loader to program SPI flash memory over JTAG.
BSCAN_SPARTAN3 …
Reading Device DNA on Spartan 3A chip
Among Spartan-3 generation of FPGAs only families 3A and 3AN have unique device identifier (device DNAs). DNA is a factory programmed unique 57-bit long number, whose the most significant bit is "1" and the second most significant bit is "0":
The Spartan 3A chip (xc3s50a) should be unconfigured (not loaded …