A Xilinx Spartan 3A chip can be programmed by using UrJTAG's pld command by fixing some issues related to old instructions. In this example, a Prometheus FPGA board is used. It is composed of a XC3S50A chip which can be configured by using FT-232H circuit's MPSSE mode. To start with, start UrJTAG and detect attached devices:
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[johndoe@ArchLinux]% jtag UrJTAG 2019.12 # Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable ft2232 pid=0x6014 vid=0x0403 driver=ftdi-mpsse Connected to libftdi driver. jtag> detect IR length: 6 Chain length: 1 Device Id: 00000010001000010000000010010011 (0x02210093) Manufacturer: Xilinx (0x093) Part(0): xc3s50a (0x2210) Stepping: 0 Filename: /usr/share/urjtag/xilinx/xc3s50a/xc3s50a |
Once the chip is recognized, one can read the values of the status register:
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jtag> pld status Status register (0x337c) SYNC_TIMEOUT 0 SEUR_ERR 0 DONE 1 INIT 1 MODE_M2 0 MODE_M1 0 MODE_M0 1 VSEL_VS2 1 VSEL_VS1 0 VSEL_VS0 1 GHIGH_B 1 GWE 1 GTS_CFG_B 1 DCM_LOCK 1 ID_ERROR 0 CRC_ERROR 0 |
Configuring of FPGA using UrJTAG's "pld" command
However, trying to configure the chip with a *.bit file will give an error:
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jtag> pld load Clock.bit Bitstream information: Design: Clock.ncd;UserID=0xADEAFBEE Part name: 3s50avq100 Date: 2017/01/21 Time: 15:37:11 Bitstream length: 54664 error: pld subsystem: unknown instruction 'JPROGRAM' |
This is caused by missing definition of JTAG commands and chip-specific registers in the corresponding UrJTAG data file (analogue of BSDL file).
Solution: define these instructions manually by looking into the necessary datasheet (UG332: "Spartan-3 Generation Configuration User Guide"):
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jtag> instruction JSHUTDOWN 001101 BYPASS jtag> instruction JSTART 001100 BYPASS jtag> instruction JPROGRAM 001011 BYPASS jtag> pld load Clock.bit Bitstream information: Design: Clock.ncd;UserID=0xADEAFBEE Part name: 3s50avq100 Date: 2017/01/21 Time: 15:37:11 Bitstream length: 54664 jtag> |
As seen from above, "pld load Clock.bit" command did not throw any errors and the FPGA was successfully programmed.
Configuring of FPGA using bit2svf and UrJTAG
Download bit2svf toolbox from the sourceforge repository. Unpack the archive:
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[johndoe@ArchLinux]% tar -xvf bit2svf-1.3.1.tar.gz |
Change into directory and modify Makefile by editing the following line:
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CFLAGS=-Wall -g3 -I$(BIDIR) |
and changing it to:
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CFLAGS=-Wall -g3 -I$(BIDIR) -I. -v -fcommon |
Now compile the toolbox:
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[johndoe@ArchLinux]% make |
Add the following line to the ./templates/DEVICES file:
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XC3S50A , 02210093, 0fffffff, alg_Spartan_3, VOID , 0l |
Convert a *.bit file into an *.svf file:
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[johndoe@ArchLinux]% ./bit2svf -p ./templates/ Clock.bit Clock.svf XC3S50A bit2svf - SVF file generator - v1.3.1 Copyright (c) 2005 Juan Pablo D. Borgna/INTI Copyright (c) 2006-2007 Salvador E. Tropea/INTI Using DEVICES: ./templates/DEVICES Using template: ./templates/alg_Spartan_3.svft Bit file created on 2017/01/21 at 15:37:11. Created from file Clock.ncd;UserID=0xADEAFBEE for Xilinx part 3s50avq100. Bitstream length is 54664 bytes. Process finsished sucefully. |
Open UrJTAG and configure the FPGA:
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[johndoe@ArchLinux]% jtag UrJTAG 2019.12 # Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable ft2232 pid=0x6014 vid=0x0403 driver=ftdi-mpsse Connected to libftdi driver. jtag> detect IR length: 6 Chain length: 1 Device Id: 00000010001000010000000010010011 (0x02210093) Manufacturer: Xilinx (0x093) Part(0): xc3s50a (0x2210) Stepping: 0 Filename: /usr/share/urjtag/xilinx/xc3s50a/xc3s50a jtag> svf Clock.svf |