Programming Xilinx Spartan 3A FPGA via UrJTAG

A Xilinx Spartan 3A chip can be programmed by using UrJTAG's pld command by fixing some issues related to old instructions. In this example, a Prometheus FPGA board is used. It is composed of a XC3S50A chip which can be configured by using FT-232H circuit's MPSSE mode. To start with, start UrJTAG and detect attached devices:

Once the chip is recognized, one can read the values of the status register:

Configuring of FPGA using UrJTAG's "pld" command

However, trying to configure the chip with a *.bit file will give an error:

This is caused by missing definition of JTAG commands and chip-specific registers in the corresponding UrJTAG data file (analogue of BSDL file).
Solution: define these instructions manually by looking into the necessary datasheet (UG332: "Spartan-3 Generation Configuration User Guide"):

As seen from above, "pld load Clock.bit" command did not throw any errors and the FPGA was successfully programmed.

Configuring of FPGA using bit2svf and UrJTAG

Download bit2svf toolbox from the sourceforge repository. Unpack the archive:

Change into directory and modify Makefile by editing the following line:

and changing it to:

Now compile the toolbox:

Add the following line to the ./templates/DEVICES file:

Convert a *.bit file into an *.svf file:

Open UrJTAG and configure the FPGA: