UrJTAG is a good low-level tool to learn boundary scan operations and play with EXTEST, INTEST instructions. Assuming that the Basys2 board is connected to a UM232H-based JTAG adapter as described in the previous article, we can test EXTEST and INTEST instructions. Note that depending on package (VQ100, CP132, TQ144), the chip may have different number of input/output pins, which changes the size of the boundary scan register (BSR). For this reason, a suitable BSDL file should be used. In our case it is xc3s100e_cp132.bsd. Let's connect the UM232H-based JTAG adapter and run UrJTAG:
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[johndoe@ArchLinux]% jtag UrJTAG 0.10 #2052 Copyright (C) 2002, 2003 ETC s.r.o. Copyright (C) 2007, 2008, 2009 Kolja Waschk and the respective authors UrJTAG is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for UrJTAG. warning: UrJTAG may damage your hardware! Type "quit" to exit, "help" for help. jtag> cable ft2232 vid=0x0403 pid=0x6014 Connected to libftd2xx driver. jtag> bsdl path Basys2_BSDL jtag> detect IR length: 14 Chain length: 2 Device Id: 11110101000001000101000010010011 (0xF5045093) Filename: Basys2_BSDL/xcf02s.bsd Device Id: 00010001110000010000000010010011 (0x11C10093) Filename: Basys2_BSDL/xc3s100e_cp132.bsd jtag> print chain No. Manufacturer Part Stepping Instruction Register ------------------------------------------------------------------------------------------------------------------- 0 XCF02S BYPASS BYPASS * 1 XC3S100E_CP132 BYPASS BYPASS jtag> part 0 jtag> instruction BYPASS jtag> shift ir jtag> print chain No. Manufacturer Part Stepping Instruction Register ------------------------------------------------------------------------------------------------------------------- * 0 XCF02S BYPASS BYPASS 1 XC3S100E_CP132 BYPASS BYPASS jtag> part 1 jtag> instruction EXTEST jtag> shift ir jtag> print chain No. Manufacturer Part Stepping Instruction Register ------------------------------------------------------------------------------------------------------------------- 0 XCF02S BYPASS BYPASS * 1 XC3S100E_CP132 EXTEST BSR jtag> # Now turn on LED-0 which is connected to pin M5 jtag> set signal M5 out 1 jtag> shift dr |
Selecting "part 0" (XCF02S PROM flash) and setting it to BYPASS mode is not necessary, since it is already in that mode. Loading "part 1" (XC3S100E FPGA chip) with EXTEST instruction will activate pull-up resistors of all LEDs on the board and they will start glowing. Note that after this procedure, the active data register is set to BSR as displayed by UrJTAG. The following operation will load only pin M5 with logic "1":
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jtag> set signal M5 out 1 jtag> shift dr |
Now let's play with 7-segment display. By setting pin F12 to logic "0", we activate the rightmost display. If we want to display digit "four" with a dot ("4.") we need to properly set all 7 segments and the dot point:
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jtag> # Rightmost display is F12 jtag> set signal F12 out 0 jtag> shift dr jtag> # 7-segments and dot point: A, B, C, D, E, F, G, DP in this order jtag> # "1" means "off" jtag> # "0" means "on" jtag> set signal L14 out 1 jtag> set signal H12 out 0 jtag> set signal N14 out 0 jtag> set signal N11 out 1 jtag> set signal P12 out 1 jtag> set signal L13 out 0 jtag> set signal M12 out 0 jtag> set signal N13 out 0 jtag> shift dr |
The board should look like this:
