Boundary Scan Operations with UrJTAG on Basys2 Development Board

UrJTAG is a good low-level tool to learn boundary scan operations and play with EXTEST, INTEST instructions. Assuming that the Basys2 board is connected to a UM232H-based JTAG adapter as described in the previous article, we can test EXTEST and INTEST instructions. Note that depending on package (VQ100, CP132, TQ144), the chip may have different number of input/output pins, which changes the size of the boundary scan register (BSR). For this reason, a suitable BSDL file should be used. In our case it is xc3s100e_cp132.bsd. Let's connect the UM232H-based JTAG adapter and run UrJTAG:

Selecting "part 0" (XCF02S PROM flash) and setting it to BYPASS mode is not necessary, since it is already in that mode. Loading "part 1" (XC3S100E FPGA chip) with EXTEST instruction will activate pull-up resistors of all LEDs on the board and they will start glowing. Note that after this procedure, the active data register is set to BSR as displayed by UrJTAG. The following operation will load only pin M5 with logic "1":

Now let's play with 7-segment display. By setting pin F12 to logic "0", we activate the rightmost display. If we want to display digit "four" with a dot ("4.") we need to properly set all 7 segments and the dot point:

The board should look like this: