Yearly Archives: 2017

There are no tutorials explaining the use of BSCAN_SPARTAN3 primitive on Xilinx FPGAs. It's a very useful feature, which allows to literally establish a PC-to-FPGA link over a JTAG adapter. This primitive is already used in projects such as xc3sprog and Papilio-Loader to program SPI flash memory over JTAG.


The GNU Debugger (GDB) is a powerful tool to debug binary executables. It can be used to do reverse-engineering as well. Let's debug the following code written by LiveOverflow:

I wanted to write a simple program in AMD64 assembly language which prints "Hello, World!". Here is the code:

Examining data stored in the memory of the program may be interesting to understand low-level mechanism of variable management and type conversions. Let's dump content of an integer bytewise:


The following setup was used for Basys2 board with an external FTDI-based JTAG adapter. Read the previous posts to get familiar with setup.

Specifying USERCODE

User code register provides bit stream identification and a type of version control. To write a user code into a bit stream in Xilinx ISE, …

In order to program Basys2 board using xc3sprog and FTDI-Based JTAG Adapter, learn positions of the devices in the chain:

UrJTAG is a good low-level tool to learn boundary scan operations and play with EXTEST, INTEST instructions. Assuming that the Basys2 board is connected to a UM232H-based JTAG adapter as described in the previous article, we can test EXTEST and INTEST instructions. Note that depending on package (VQ100, CP132, …