SVF Tutorial: Header and Trailing Registers Explained

Objective

This tutorial concerns with explaining use of some basic Serial Vector Format (SVF) instructions assuming that you are familiar with JTAG and TAP.

As an example, reading ID codes of the devices in a JTAG chain of the Digilent Basys2 FPGA board is given. A generic FTDI-MPSSE-based JTAG adapter was used and the tests were conducted in OpenOCD.

The Board and its JTAG Chain

Here is the JTAG chain of the Digilent Basys2 FPGA board:

The first IC (xc3s100e) is the actual FPGA chip from the Spartan 3E family. The second chip (xcf02s) is a flash memory (PROM). For each chip, JTAG-specific instructions and properties of special registers including BSR (boundary scan register) are provided in BSDL files. These files can be retrieved from the vendor's website or from the Xilinx ISE installation. If you have Xilinx ISE already installed, check out the "xc3s100e.bsd" file located at "$XILINX_ISE_PATH/spartan3e/data/" and "xcf02s.bsd" file located at "$XILINX_ISE_PATH/xcf/data/", where $XILINX_ISE_PATH  is the installation path, e.g. "/opt/Xilinx/10.1/ISE/".

From the "xc3s100e.bsd" and "xcf02s.bsd" we can learn the Instruction Register lengths
and opcodes for instructions:

Device IR Length BYPASS IDCODE
xc3s100e 6 bits 111111 001001
xcf02s 8 bits 11111111 11111110

ID code register is always 32 bit long. Required in the standard.
ID code of the xc3s100e device is a 32-bit sequence:
0b(XXXX 0001 1100 0001 0000 0000 1001 0011) == 0x(?1C10093), where 4 most significant bits, denoted by "XXXX", represent version and aren't important.

ID code of the xcf02s device is a 32-bit sequence:
0b(XXXX 0101 0000 0100 0101 0000 1001 0011) == 0x(?5045093), where 4 most significant bits, denoted by "XXXX", represent version and aren't important.

These ID codes can be checked using Digilent's official configuration tools:

Methods to read ID codes of the devices:

  1. Put both devices into RESET state. According to JTAG specifications, all devices in the chain must choose ID code register as data register. Shift any 64-bit long sequence into TDI while in "ShiftDR" state and observe concatenated pair of ID codes [Spartan 3E, PROM] = "0x?1C10093?5045093" at TDO. Least significant bit (LSB) comes first.
  2. Load Spartan 3E's instruction register with IDCODE instruction, and load PROM's instruction register with BYPASS instruction. ID code register will be selected as Spartan 3E's data register and a 1-bit long bypass register will selected as PROM's data register. Shift a 32+1 bit long sequence into TDI while in "ShiftDR" state, at the TDO output observe ID code of Spartan 3E padded with an extra bit at LSB position: "0x163820126" (see the explanation in the code below).
  3. Similarly to option (2), but now PROM will be loaded with IDCODE instruction and Spartan 3E will be bypassed. The scanned out 33-bit long sequence will consist of ID code and an extra bit at MSB position: "0x1?5045093".

All explanations are given in the comments, read them carefully:

The output should look like this:

 

References

XAPP503 "SVF and XSVF File Formats for Xilinx Devices" application note by Xilinx.

Serial Vector Format Specification by ASSET InterTech, Inc.

One thought on “SVF Tutorial: Header and Trailing Registers Explained

  1. Antonio Farthing

    Hi- When SVF files are generated to perform the "verify" operation, what information is used? Is there a checksum or specific state the ID code register must be active?

    Thanks in advance,
    -Tony

    Reply

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